Generally, one of the methods for improving the quality of a television image involves increasing the number of scanning lines as well as increasing the number of horizontal pixels. For example, a video signal of the current NTSC system has a vertical resolution of about 300 lines owing to interlaced scanning at 2:1. The CRT used in the typical television receiver has 525 scanning lines, and a lower resolution due to interlaced scanning, for which there is known a method of improving the resolution in a vertical direction by increasing the number of pixels in the vertical direction through the field interpolation using a field buffer to make non-interlace.
Some CRTs used in the high definition television receivers have a set number of horizontal pixels about twice as many as that of the CRTs of the ordinary television receivers, and thus, there is known a method for improving the resolution in a horizontal direction by doubling the number of pixels in a scanning line direction by interpolation.
By the way, when the number of vertical pixels is to be increased in order to improving the quality of a television image as described above, a field buffer having a large capacity is required for interpolation, which leads to a problem with the larger circuit. In particular, the interpolation process in the horizontal direction and the interpolation process in the vertical direction are required to be effected in a short time, for example, within 1/60 seconds for one screen. Therefore, there is a need for an image processing circuit capable of performing the interpolation processes in the horizontal and vertical directions at high speed with hardware of simple structure without making arithmetic operation by the processor.